Schedule
Lecture recordings are available through Panopto after class (login required).
For readings, P&H refers to Computer Organization and Design. H&P refers to Computer Architecture: A Quantitative Approach.
Jump to assignment schedule (Includes quizzes)
Lecture schedule
| 1/30 | Build a CPU: more instruction types | P&H 4.3 | HW1e due (1/29) |
| 1/28 | Build a CPU: I-type instructions (worksheet) | P&H 4.1-4.2 | HW1a-d due (1/27) |
| 1/26 | Hardware principles | P&H A.1-A.3, first part of A.4 (up to but not including “Datatypes and Operators in Verilog”), A.7-A.8. Optionally, C.1-C.2. | |
| 1/23 | RISC-V assembly | P&H 2.1-2.2, 2.4-2.6 | |
| 1/21 | What is architecture; bits | HW0/HW1 out |
Assignment schedule
All due dates are 11pm Eastern and exclusive of late days. All quizzes are in class (10am-10:25am).
- HW1: out 1/21; due 1/27, 1/29, and 2/4 (see HW1 page for details)
- HW2: out 2/6, due 2/18, quiz 2/23
- HW3: out 2/20, due 3/4, quiz 3/9
- HW4: out 3/6, due 3/18, quiz 4/1
- HW5: out 4/3, due 4/15, quiz 4/20