Lecture recordings are available through Panopto after class (login required).

For readings, P&H refers to Computer Organization and Design. H&P refers to Computer Architecturer: A Quantitative Approach.

Day Topic Readings Assignments
2/21 TLBs   HW3 out, HW2 due
2/19 Virtual memory P&H 5.7  
2/14 Cache performance and associativity P&H 5.4  
2/12 Cache controllers P&H 5.3  
2/10 Memory hierarchy P&H 5.1-5.2  
2/7 Build a CPU: pipeline hazards P&H 4.6-4.8 HW2 out, HW1 due
2/5 Build a CPU: control; motivating pipelining P&H 4.5  
2/3 Build a CPU: memory and control P&H 4.3-4.4 HW1f out, HW1e soft due date
1/31 Build a CPU: arithmetic instructions P&H 4.1-4.2 HW1e out, HW1d soft due date
1/29 Hardware principles P&H A.1-A.3, first part of A.4 (up to but not including “Datatypes and Operators in Verilog”), A.7-A.8. Optionally, C.1-C.2. HW1d out, HW1c soft due date
1/27 RISC-V assembly P&H 2.1-2.2, 2.5-2.6 HW1c out, HW1b soft due date
1/24 Data representations P&H 2.4 HW1a,b out
1/22 Welcome/What is architecture?   HW0 out

Homework schedule (homeworks due at 10pm. These deadlines do not include the late days).

  • HW1: Out in stages starting 1/22, due 2/7
  • HW2: Out 2/7, due 2/21
  • HW3: Out 2/21, due 3/7
  • HW4: Out 3/7, due 3/21
  • HW5: Out 3/31, due 4/14

Project proposals (short group assignment): Due 3/19