Lecture recordings are available through Panopto after class (login required).

For readings, P&H refers to Computer Organization and Design. H&P refers to Computer Architecture: A Quantitative Approach.

Final project information

Day Topic Readings Assignments
4/23 Failures, etc See links in slides for further reading  
4/21 Memory technologies: past and future    
4/18 Green Computer Architectures    
4/16 Energy, power, and other trends H&P 1.5. See also resources linked on last slide, especially P&H “A new golden age for computer architecture” HW5 due
4/14 GPU memory    
4/11 Execution on GPUs P&H B.5, B.8, refer to Cuda documentation  
4/9 SPMD & GPUs (Use as a reference – this appendix is long!) P&H B.1-B.4  
4/7 SIMD in modern computers H&P 4.3  
4/4 Vector processors    
4/2 Data-level parallelism H&P 4.2 HW5 out
3/31 Thread-level parallelism H&P 3.12  
3/21 Spectre and dead uops See first slide HW4 due
3/19 Compilers for architects H&P H.4-H.5  
3/17 Superscalar; OOO IRL H&P 3.8  
3/14 Branch prediction H&P 3.3-3.4  
3/12 Speculative algorithm    
3/10 Speculative execution H&P 3.6  
3/7 Tomasulo’s algorithm H&P 3.5 HW4 out, HW3 due
3/5 ILP and dependences H&P (not P&H) 3.1  
3/3 ISAs revisited P&H 2.21; the two papers from slides  
2/28 I/O and exceptions P&H 4.9,6.9  
2/26 Perils of shared caches (coherence, side channels) P&H 5.10  
2/24 Cache tradeoffs P&H 5.8, 5.10  
2/21 TLBs   HW3 out, HW2 due
2/19 Virtual memory P&H 5.7  
2/14 Cache performance and associativity P&H 5.4  
2/12 Cache controllers P&H 5.3  
2/10 Memory hierarchy P&H 5.1-5.2  
2/7 Build a CPU: pipeline hazards P&H 4.6-4.8 HW2 out, HW1 due
2/5 Build a CPU: control; motivating pipelining P&H 4.5  
2/3 Build a CPU: memory and control P&H 4.3-4.4 HW1f out, HW1e soft due date
1/31 Build a CPU: arithmetic instructions P&H 4.1-4.2 HW1e out, HW1d soft due date
1/29 Hardware principles P&H A.1-A.3, first part of A.4 (up to but not including “Datatypes and Operators in Verilog”), A.7-A.8. Optionally, C.1-C.2. HW1d out, HW1c soft due date
1/27 RISC-V assembly P&H 2.1-2.2, 2.5-2.6 HW1c out, HW1b soft due date
1/24 Data representations P&H 2.4 HW1a,b out
1/22 Welcome/What is architecture?   HW0 out

Homework schedule (homeworks due at 10pm. These deadlines do not include the late days).

  • HW1: Out in stages starting 1/22, due 2/7
  • HW2: Out 2/7, due 2/21
  • HW3: Out 2/21, due 3/7
  • HW4: Out 3/7, due 3/21
  • HW5: Out 4/2, due 4/16

Project abstracts and hypotheses (short group assignment): Due 4/11

Project report: Due 5/5