Lecture recordings are available through Panopto after class (login required).

For readings, P&H refers to Computer Organization and Design. H&P refers to Computer Architecturer: A Quantitative Approach.

Final project information

Day Topic Readings Assignments
4/24 Unconventional computing IBM Quantum Courses (if interested)  
4/22 EE and Memory See last slide  
4/19 Capabilities Introduction to CHERI Project abstracts/hypotheses due
4/17 Topics in Architecture Research Clockhands, UPMEM-PIM, Phantom  
4/15 Energy, Power, and other trends H&P 1.5  
4/12 GPU memory    
4/10 Execution on GPUs P&H B.5, B.8, refer to Cuda documentation  
4/8 SPMD & GPUs (Use as a reference – this appendix is long!) P&H B.1-B.4  
4/5 SIMD in modern computers H&P 4.3 HW5 out
4/3 Assessing vector processors    
4/1 Data-level parallelism H&P 4.2  
3/20 Thread-level parallelism H&P 3.12  
3/18 Compilers and Hardware H&P H.4-H.5 HW4 due (10pm Tues)
3/18 Compiler-supported ILP H&P 3.2  
3/15 Superscalar H&P 3.8  
3/13 Speculation H&P 3.6  
3/11 Tomasulo’s algorithm H&P 3.5  
3/8 Advanced branch prediction; OOO H&P 3.3-3.4  
3/6 ILP and dependences H&P (not P&H) 3.1 HW4 out, HW3 due (10pm Tues)
3/4 Side channels    
3/1 ISAs revisited P&H 2.21; the two papers from slides  
2/28 I/O P&H 4.9,6.9  
2/26 Cache tradeoffs and metrics P&H 5.8  
2/23 Virtual Memory and TLBs P&H 5.7  
2/21 Cache coherence, synchronization, and consistency P&H 5.10 HW3 out, HW2 due
2/16 Cache performance and associativity P&H 5.4  
2/14 Cache controllers P&H 5.3  
2/12 Memory hierarchy P&H 5.1-5.2  
2/9 Build a CPU: pipeline hazards P&H 4.6-4.8  
2/7 Build a CPU: motivating pipelining P&H 4.5 HW2 out, HW1 due
2/5 Build a CPU: memory and control P&H 4.3-4.4; Step 3 of notes from 2/2 lecture HW1e out, HW1d soft due date
2/2 Build a CPU: arithmetic instructions P&H 4.1-4.2 HW1d out, HW1c soft due date
1/31 Hardware principles P&H A.1-A.3, first part of A.4 (up to but not including “Datatypes and Operators in Verilog”), A.7-A.8. Optionally, C.1-C.2. HW1c out, HW1b soft due date
1/29 RISC-V assembly P&H 2.1-2.2, 2.5-2.6 HW1b out
1/26 Data representations P&H 2.4 HW1a out
1/24 Welcome/What is Architecture?   HW0 out